Answers Database
A1.5 Par - Design hangs in PAR after optimization.
Record #4626
Product Family: Software
Product Line: FPGA Implementation
Product Part: par
Problem Title:
A1.5 Par - Design hangs in PAR after optimization.
Problem Description:
A case has been seen where PAR hangs after optimization.
The problem is in the KPATHS timing algorithm which is
new for A1.5.
Solution 1:
The problem can be avoided by switching to the DFS timing
algorithm which was the default algorithm in A1.4.
setenv XILINX_GRAPHIMP DFS (workstations)
set XILINX_GRAPHIMP=DFS (PCs)
This problem was fixed for 1.5i.
End of Record #4626 - Last Modified: 04/30/99 12:02 | 
