Answers Database
FPGA Express 2.1.3: Error: Clock variable is being used as data (HDL-175).
Record #4629
Product Family: Software
Product Line: Synopsys
Product Part: FPGA Express
Product Version: 2.1.2
Problem Title:
FPGA Express 2.1.3: Error: Clock variable is being used as data (HDL-175).
Problem Description:
Urgency: Standard
General Description:
When synthesizing a design using FPGA Express v2.x, the following error may occur:
Error: Clock variable 'CLK' is being used as data . (HDL-175)
This error will occur if the signal 'CLK' is used as both a clock signal and regular data.
Solution 1:
This issue has been resolved for most cases in FPGA Express 3.0 and newer.
However, some issues of this type still exist and are scheduled to be fixed in a future
release of FPGA Express software.
End of Record #4629 - Last Modified: 11/09/99 14:00 |
