Answers Database
M1.5,bufg,vhdl: Logic trimmed when all buffers instantiated rather than placed by Express.
Record #4642
Product Family: Software
Product Line: FPGA Implementation
Product Part: map
Product Version: 1.5
Problem Title:
M1.5,bufg,vhdl: Logic trimmed when all buffers instantiated rather than placed by Express.
Problem Description:
Urgency: Standard
General Description:
In Express 2.x, when the 'Do not insert I/O Pads' option is selected
(FPGA Express), or the 'Insert I/O pads' is de-selected (Foundation Express),
after instantiating clock buffers manually, the buffered clk signal (output of
a BUFGLS) produces the following message from the Mapper (in M1.5):
Translate:
WARNING: basnu:111-logical net "clk_in" has no driver.
Map:
ERROR:baste:314 - NCD was not produced. All logic was removed from design.
This is usually due to having no input or output PAD connections in the
design and no nets or symbols marked as 'SAVE'. You can either add PADs or
'SAVE' attributes to the design, or run 'map -u' to disable logic trimming
in the mapper.
This causes all clocked logic to be trimmed.
The other nets, with instantiated I/O buffers do not generate warnings.
Solution 1:
While synthesizing the HDL code, allow Express to insert I/O pads/buffers
(which is the default), even though all the I/O buffers have been instantiated
in the source HDL. The implementation works fine (additional buffers are not
incorrectly added).
Solution 2:
For F1.4 (Express 2.03), there are 2 options:
1. Allow Express to 'insert pads' (keep 'Do not insert I/O pads' deselected). Express will produce w
arning messages such as:
Warning: Existing pad cell '...' is connected to the port '...' - no pads cells inserted at this por
t. (FE-PADMAP-1)
This warning can be ignored, since it is just notifying you that it already found a buffer for the p
ort in question. No unrequired buffers will be inserted.
2. At the bottom of the Express netlist (design.xnf) there will be a list of SIG records. You can ch
ange the SIG record for the clock to an EXT record.
Then save the modified .xnf file and use it for implementation (M1).
Sig -> Ext modification:
Change the SIG record to an EXT record as shown below.
SIG, clk_in, PIN=clk_in
EXT, clk_in, I
End of Record #4642 - Last Modified: 11/02/98 15:15 |
