Answers Database LogiCORE PCI32 4000: VHDL synthesis/simulation with PCI LogiCORE v2.0, Exemplar Leonardo v4.2.2 & M1.4.12 Record #4647 Product Family: Software Product Line: LogiCore Product Part: PCI Core Generator Product Version: 2.0 Problem Title: LogiCORE PCI32 4000: VHDL synthesis/simulation with PCI LogiCORE v2.0, Exemplar Leonardo v4.2.2 & M1.4.12 Problem Description: Urgency: Standard General Description: Tactical Solution only, to run PCI LogiCORE through Exemplar Leonardo 4.2.2 The PCI LogiCORE v2.0 can be implementend in the VHDL synthesis/simulation flow in M1.4.12 using Exemplar Leonardo 4.2.2. For more information about the PCI LogiCORE, see http://www.xilinx.com/products/logicore/pci/pci_sol.htm. In this example, a design called 'ping' is used to demonstrate using the PCI LogiCORE v2.0 in this VHDL synthesis flow. In a 'real' design, the 'ping' design is replaced with the customer application. Note: it assumed that the user has already setup the environment for running M1.4.12 and Exemplar Leonardo 4.2.2. Exemplar Leonardo is not a HDL simulation tool. There is a VHDL simulation flow in M1.4.12. When describing functional and timing simulation, a general flow will be described. For simulating the PCI LogiCORE v2.0 in M1.4.12, use MTI. For this example, it is assumed that the user has already downloaded the PCI LogiCORE v2.0, and has unzipped the contents in a directory called 'pcim' in the root directory. If a target core had been downloaded, the directory created would have been 'pcis'. The PCI LogiCORE v2.0 contains files for a master, slave, and implementation files for the 4013XLT, 4028XLT, and 4062XLT. For this solution record, the 4013XLT is used and the PCI LogiCORE configured as a master is assumed. Solution 1: Functional simulation with the PCI LogiCORE v2.0 and M1.4.12. (1) Get a list of files needed to functionally simulate the PCI LogiCORE. At the root directory of your system, type: cd c:\pcim\vhdl_exp\example\func_sim (2) The func_sim directory in the generic VHDL path (c:\pcim\vhdl\example\func_sim) will contain a file called analyze_ping, which lists the files needed for functional simulation. The default list of files are located relative to the generic func_sim directory. The files needed for functional simulation are: ..\..\src\xpci\pci_lc_i.vhd -Simulation model for the PCI LogiCORE v2.0 ..\..\src\xpci\pcim_lc.vhd -Simulation model for the PCI LogiCORE v2.0 ..\source\cfg.vhd -Used for configuration of PCI LogiCORE v2.0 ..\source\ping.vhd -User application ..\source\pcim_top.vhd -Top-level file which connnects core to ping ..\source\dumb_target.vhd -signal generation for testbench ..\source\dumb_arbiter.vhd -signal generation for testbench ..\source\stimulus.vhd -signal generation for testbench ..\source\ping_tb.vhd -testbench For a user design, the ping.vhd file is replaced with the user VHDL code. At a minimum cfg.vhd, pcim_lc.vhd, and pci_lc_i.vhd must always be used. (3) Setup your VHDL simulator to use to the VITAL simulation library in M1.4.12. The VITAL simulation library is located at %XILINX%\vhdl\src (4) Functionally simulate the PCI LogiCORE v2.0 by processing the list of files in step (2) into the VHDL simulator. Solution 2: Synthesis/Place & Route of the PCI LogiCORE v2.0 with Exemplar Leonardo and M1.4.12 (1) Assuming that 'pcim' is installed in your root directory, copy the following VHDL files into a directory of your choice. For this example. the directory is c:\mypci: copy c:\pcim\vhdl_exp\example\source\ping.vhd c:\mypci copy c:\pcim\vhdl_exp\example\source\cfg.vhd c:\mymci copy c:\pcim\vhdl_exp\example\source\pcim_top.vhd c:\mypci (2) Start Exemplar Leonardo. Check that the working directory is set to directory where the VHDL files reside. The working directory is displayed on the top bar of the Leonardo main window. To change the working directory you can type cd c:\mypci at the Leonardo prompt, or select File -> Change Working Directory, then browse to the appropriate directory. (3) Start the Toolbar or Flow Guide by clicking on either the Toolbar button or the Flow Guide button just below the pull-down menus. (4) Load the appropriate library by clicking on the Load Library button. Choose the Xilinx 4000XL library, and click on the Load button at the bottom of the Load Library window. --- Insert GIF --- (5) Load the technology Module generator by clicking on the Load Modgen button. Select Xilinx 4e and click on the Load button. (6) Read in the source HDL files by clicking on the Read button. The Read window will come up. Specify the list of files by clicking on the multiple sheet icon all the way to the right of the Filename row. The Input File List Editor window will come up. Click on the Add button, and the Open window will come up. You can now highlight the HDL files to be read in by using a combination of left-mouse-button and the ctrl-key and/or shift-key. Once the appropriate files are highlighted click on the Open button. (7) Change the order of the files being read in. Now the files should be listed in the Input File List Editor window, but the files must be read in from the bottom up. To change the the listing to the appropriate order highlight the file pcim_top.vhd, select the bottom option, then click the Move button. The file list should now look like the following. Click on the OK button to close the Input Files List Editor after the appropriate changes have been made. (8) Read the files in by clicking on the Read button. The default options can be used in this Read window. (9) Optimize the design. The design must be optimized as a macro since all the necessary I/O are instantiated in the code. To do this Select the option for the Mode: Macro. Default options can be used for everything else. To Opimize the design click on the Optimize button. (10) Before writing out the XNF files, the lower case characters must be converted to upper case in order to match the guide file naming. To do this you can select Utilities -> Convert Lower to Upper Case, and the lo2up window will come up. Object Type shold be set to all. Click on the lo2up icon to finish this process. Another way to do this is just after Optimize, at the Leonardo prompt type the following: lo2up all NOTE: Not converting the lower case characters to upper case will result in the guide file name not matching up. This will result in the design not meeting timing. (11) Write the XNF netlists by clickin on the Write button, and the Write window will come up. By default it will write to the working directory, so in the Write window you can just type pcim_top.xnf. To specify where to write the file to a directory of choice click on the open file icon just to the right of the Filename dialogue box. the Save As window will come up, and here you can select the appropriate directory and give the File name of pcim_top.xnf. When the appropriate information is selected click the Save button and the Save As window will close. Now in the Write window the full path including the name given will be shown. Select the Format to be XNF. To write the files out click on the Write button in the Write window. the following files will be written: pcim_top.xnf cfg.xnf ping.xnf (12) Copy the following files into the c:\mypci directory: copy c:\pcim\vhdl_exp\src\xpci\pcim_lc.xnf c:\mypci\pcim_lc.xnf copy c:\pcim\vhdl_exp\src\xpci\pci_lc_i.ngo c:\mypci copy c:\pcim\vhdl_exp\src\ucf\m13xp208.ucf c:\mypci copy c:\pcim\vhdl_exp\src\guide\m13xp208.ncd c:\mypci pcim_lc.xnf must always be used. This file merges the core with the design correctly and contains needed constraints. pci_lc_i.ngo is the PCI LogiCORE v2.0 design. A constraint file included with the PCI LogiCORE v2.0 must be used. There are four constraint files in the c:\pcim\vhdl_exp\src\ucf directory. There are two UCF files for the 4013XLT, one for the 4028XLT, and three for the 4062XLT. The 4013xltpq208 guide file was used in this example. (13) Place and route the the design by running the following commands in the c:\mypci directory. Optionally, the listed commands below can be placed in a batch file: set XIL_MAP_LOC_CLOSED=true ngdbuild -p 4013xlpq208-1 -uc c:\mypci\s13xp208_1.ucf pcim_top.xnf map pcim_top.ngd -o pcim_top.ncd pcim_top.pcf par -gm exact -gf c:\mypci\m13xp208.ncd -l 4 -d 1 -w pcim_top pcim_top_routed pcim_top trce -v 10 pcim_top_routed pcim_top ngdanno pcim_top_routed ngd2ver -w pcim_top_routed Once PAR has finished check the pcim_top_routed.par file and search for "comps". This will show how many of the comps are guided properly during PAR (place and route). The required number of comps guided for the XC4013XL is 101 out of 698 and for the Xc4062XL is 47 out of 698. The Timing Score should be (0) after a number of router iterations. NOTE: Multiple cost table may have to be run. If after the first run you do not get a Timing Score (0) nor the proper number of comps guided, then you may have to use another cost table. To use a different cost table use the PAR option -t to specify a different starting cost table, (i.e. par -t 2...) Solution 3: Timing Simulation with the PCI LogiCORE v2.0 and M1.4.12. (1) After place and route, a structural VHDL file, pcim_top_routed.vhd, and an SDF file, pcim_top_routed.sdf, will be in the c:\mypci directory. (2) Setup your VHDL simulator to use the M1.4.12 VHDL simulation libraries, which are located in %XILINX%\dl\src. (3) Simulate the PCI LogiCORE design, by reading in the pcim_top_routed.vhd file, pcim_top_routed.sdf file, and testbench file into the VHDL simulator. In this case for the ping design, the 'testbench' is comprised of the following files: c:\pcim\vhdl_exp\example\source\ping_tb.vhd c:\pcim\vhdl_exp\example\source\stimulus.vhd c:\pcim\vhdl_exp\example\source\dumb_target.vhd c:\pcim\vhdl_exp\example\source\dumb_arbiter.vhd End of Record #4647 - Last Modified: 10/01/99 14:40

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