Answers Database


M1.5 MAP : PAR fails to meet timing in M1.5 when it had in M1.4.


Record #4657

Product Family: Software

Product Line: FPGA Implementation

Product Part: par

Product Version: 1.5

Problem Title:
M1.5 MAP : PAR fails to meet timing in M1.5 when it had in M1.4.


Problem Description:
Urgency : Standard

General Description:
A design run in 1.5 failed timing specs whereas it passed in 1.4
The design met timing when map was given some optimization switches.


Solution 1:


Try the following modifications to the implementation template
1. map -cm speed
2. map -os speed -oe high
3. map -os speed -oe high -cm speed




End of Record #4657 - Last Modified: 10/30/98 13:14

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Technical Tips!