Answers Database
A1.5/F1.5 5200 PAR - Problems with placement of TBUFs when the F5_MUX is used.
Record #4658
Product Family: Software
Product Line: FPGA Implementation
Product Part: par
Product Version: 1.5
Problem Title:
A1.5/F1.5 5200 PAR - Problems with placement of TBUFs when the F5_MUX is used.
Problem Description:
URGENCY: Hot
PROBLEM LONG DESCRIPTION:
PAR is not checking the validity of the placement of TBUFs when the F5_MUX is used.
When targeting a 5200 device, TBUFs must be placed so that their source is from the adjacent CLB. H
owever, PAR places TBUFs so that they cannot be sourced from the adjacent CLB.
This problem is caused by the placement of two 5-bit functions using the F5_BUXs in the CLB along wi
th more TBUFs than can be sourced by the CLB. When 2 F5_MUXs are placed in a CLB, this leaves only
2 possible through-routes for TBUFs that are not sourced by the F5_MUXs. However, PAR will sometime
s place 3 or 4 TUBs at the CLB eventhough only 2 of them can be routed.
Solution 1:
RESOLUTION:
The workaround to this problem is to manually check and manually re-arrange the TBUFs in the design
in EPIC.
A fix for this problem will be in the M1.5i Performance Pack Update due to
begin shipping in December 1998.
End of Record #4658 - Last Modified: 10/30/98 13:07 |
