Answers Database
map 1.4:ERROR:baste:263 - The LOC constraint "P21" (a IOB location) is not valid..
Record #4678
Product Family: Software
Product Line: FPGA Implementation
Product Part: map
Problem Title:
map 1.4:ERROR:baste:263 - The LOC constraint "P21" (a IOB location) is not valid..
Problem Description:
Urgency: Hot
General Description:
Trying to source a global clock buffer from a non-dedicated clock I/O. In VHDL, by making a signal
assignment to the input signal in order to force an ibuf
between the input signal and the clock buffer.
When the design is run through MAP, M1 falls over with the error:
ERROR:baste:263 - The LOC constraint "P21" (a IOB location) is not valid for
symbol "reset_200msn.PAD" (pad signal=reset_200msn), which is being mapped
to the following site types: CLKIOB
Solution 1:
Leonardo optimizes the ibuf out which is reflected in the resulting netlist.
The reason this has occurred is because the netlist dictates
that the clock signal comes into the device and directly into
the input of a global buffer. However, because the clock
signal is not placed to an IOB with this direct access to a
global buffer, this is an illegal connection.
The solution is to insert an input buffer between the pad and
the global buffer.
End of Record #4678 - Last Modified: 10/30/98 12:27 |
