Answers Database
A1.5/F1.5 Virtex Map reports that an output is not connected, but does not trim the logic: Warning:xvkdr - blockcheck
Record #4679
Product Family: Software
Product Line: FPGA Implementation
Product Part: map
Problem Title:
A1.5/F1.5 Virtex Map reports that an output is not connected, but does not trim the logic:
Warning:xvkdr - blockcheck
Problem Description:
Urgency: Standard
General Description:
Targetting Virtex 50 PQ240 in M1.5.19 MAP, it reports that there are dangling
or non connected outputs, but it does not trim the logic associated with it. Some
of the warnings are as follows:
WARNING:xvkdr - blockcheck: Dangling CY0F input. CY0F of comp count_c[10]
is configured to use pin F1, but pin F1 is not connected.
WARNING:xvkdr - blockcheck: Dangling CY0G input. CY0G of comp count_c[10]
is configured to use pin G1, but pin G1 is not connected.
WARNING:xvkdr - blockcheck: Dangling CEMUX input. CEMUX of comp count_c[10]
is configured to use pin CE, but pin CE is not connected.
WARNING:xvkdr - blockcheck: Dangling CY0F input. CY0F of comp count_c[4]
is configured to use pin F1, but pin F1 is not connected.
WARNING:xvkdr - blockcheck: Dangling CY0G input. CY0G of comp count_c[4]
is configured to use pin G1, but pin G1 is not connected.
Solution 1:
This problem has been fixed in version 1.5i.
End of Record #4679 - Last Modified: 04/26/99 09:28 |
