Xilinx Answer #4689 : FPGA Express 2.x, HDL-178: Bus slices are not supported in sensitivity list

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FPGA Express 2.x, HDL-178: Bus slices are not supported in sensitivity list

Record #4689
Product Family: Software

Product Line: Synopsys

Product Part: FPGA Express

Product Version: 2.1.2

Problem Title:
FPGA Express 2.x, HDL-178: Bus slices are not supported in sensitivity list

Problem Description:
Urgency: Standard

General Description:
In Express 2.1, if a bus slice is being read within a process, a warning is
produced by express that a signal is being read, but is not part of the
sensistivity list. However, if the bus slice (eg bob(2 downto 1)) is placed in
the sensitivity list, express will produce a warning:

Warning L69/C0 : #0 Warning: Only simple variables are checked in the sensitivity list. The variable in the sensitivity list on line 69 will be ignored. (HDL-178)

Solution 1:

Bus slices are not allowed in sensitivity lists. To properly code the design,
one must assign a dummy signal to the bus slice (combinatorially), then replace the bus slice in the process and sensitivity list with the dummy signal.

Workaround:
1. Create dummy signals for each bit of the bus slice in question.
2. Assign the bus slice bits to these dummy signals with combinatorial logic.
3. Within the sensitivity list and process in question, replace any references
to the bus slice with the dummy signals (only in the processes in which you are trying to read from the bus slice).

Example:

architecture CFG_arch of CFG_REG is

-- Added for workaround *******************************
signal dummy_net : std_logic;

begin
-- Added for workaround ******************************
dummy_net <= is_sel(0);

-- original sensitivity list
-- process (cfg, is_sel(0))
-- workaround sensitivity list - uses redirected signal for bus slice *******
process (cfg, dummy_net)

   begin
     if cfg='1' then

-- original assignment
-- db(2) <= is_sel(0);
-- Redirected Bus bit used in place of slice - workaround ****
       db(2) <= dummy_net;

     else
       db(2) <= 'Z';
     end if;

   end process;

end CFG_arch;

Solution 2:

When accessing an entire bus within a process, it is necessary to include it in the sensistivity lis t. This is fine, as long as the correct syntax is used:

Incorrect syntax:
process (a, b, bob(3 downto 0))

Correct syntax:
process (a, b, bob);

End of Record #4689 - Last Modified: 10/20/98 09:52

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