Xilinx Answer #4697 : F1.4, XVHDL: Assigning power mode to output signals in VHDL

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F1.4, XVHDL: Assigning power mode to output signals in VHDL

Record #4697
Product Family: Software

Product Line: Metamor

Product Part: Foundation Metamor

Problem Title:
F1.4, XVHDL: Assigning power mode to output signals in VHDL

Problem Description:

Urgency: Standard

General Description:
When assigning power mode in VHDL for a CPLD design using the PWR_MODE attribute in an XVHDL (Metamo r) VHDL file gives the following warning:

WARNING:basnu:159 - Attribute "PWR_MODE" on "we_n" is on the
wrong type of object. Please see the "Attributes, Constraints, and Carry Logic" section of the Lib raries Guide for more information on this attribute.

Solution 1:

The workaround is to create intermediate nodes/signals and place the
PWR_MODE attribute on the intermediate nodes/signals.

VHDL Example:

library METAMOR;
use METAMOR.attributes.all;

entity power is

port ( DISPA : out STD_LOGIC_VECTOR (6 downto 0);
      DISPB : out STD_LOGIC_VECTOR (6 downto 0)
       ) ;
end power;

architecture fib_arch of fib is

signal mydispa, mydispb : std_logic_vector (6 downto 0);
    ATTRIBUTE PWR_MODE:STRING;

    ATTRIBUTE CRITICAL OF mydispa: SIGNAL IS TRUE;
    ATTRIBUTE PWR_MODE OF mydispa: SIGNAL IS "LOW";

    ATTRIBUTE CRITICAL OF mydispb: SIGNAL IS TRUE;
    ATTRIBUTE PWR_MODE OF mydispb: SIGNAL IS "STD";
.
.
.

DISPA <= mydispa;
DISPB <= mydispb;

end power_arch ;

End of Record #4697 - Last Modified: 01/03/00 10:59

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