Answers Database
A1.5/F1.5 PAR - PAR ignores constraint in pcf file for IOB placement
Record #4778
Product Family: Software
Product Line: FPGA Implementation
Product Part: par
Product Version: 1.5
Problem Title:
A1.5/F1.5 PAR - PAR ignores constraint in pcf file for IOB placement
Problem Description:
Urgency: Standard
General Description : Some pin locking constraints entered directly into the physical constraints fi
le (.pcf file) are ignored by par. The resulting placement has a constrained component placed in a d
ifferent IOB than the one indicated in the .pcf file.
Solution 1:
Detailed Description :
If the design contains an off-chip signal which is being routed to a global clock, and the user manu
ally inputs the pin locking constraint into the .pcf file, par will ignore it if the IPAD is directl
y connected to a BUFG and the desired IOB is not a dedicated global clock pad.
Under the above circumstances, par will not generate any warnings or errors about the invalid constr
aint in the .pcf file and will place the IOB wherever there is a free global clock IOB.
Work-around:
There are two work-arounds.
First, the constraint can be entered into the .ucf file instead of the .pcf file. This results only
in an error message being issued about the invalid constraint.
Second, an IBUF can be inserted between the IPAD and BUFG. This allows the designer to use the same
.pcf file and results in correct placement of the constrained component.
End of Record #4778 - Last Modified: 10/30/98 10:50 |
