Answers Database


COREGEN: Output of Delay Element module does not change in simulation if CE is unconnected


Record #4831

Product Family: Software

Product Line: Coregen

Product Part: Coregen

Problem Title:
COREGEN: Output of Delay Element module does not change in simulation if CE is unconnected


Problem Description:
Urgency: standard

General Description:
Output of COREGEN Delay Element module does not change in
simulation.


Solution 1:

The Delay Element does not float its CE input to VCC if left
unconnected. The signal tied to this pin is used internally
to activate the WE pin of the RAM used to store the input
to the Delay Element.

CE should always be tied either to VCC or to a control signal
whose logic level is defined--it will not respond to a clock
input unless its CE pin is driven to a logic 1 level.





End of Record #4831 - Last Modified: 10/16/98 11:47

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Technical Tips!