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LogiCORE PCI: How does the PCI CORE handle wait states between data phases?
Record #4855
Problem Title:
LogiCORE PCI: How does the PCI CORE handle wait states between data phases?
Problem Description:
Urgency: Standard
General Description:
How does the PCI CORE handle insertion of wait states between
data phases?
Solution 1:
As a Target, the core can not insert subsequent latency (wait states)
in between data phases, but can insert initial latency. The LogiCORE
target can handle the both initial and subsequent master latency
insertion (wait states inserted by the master in the beginning or
during a transfer) correctly. This is true for both Target Read and
Target Write. Target initiated wait states allow a user application
additional time before the first data transfer.
The User application can deassert the S_READY output to insert wait
states.
The Target is required to complete the first data phase of a
transaction within 16 clocks from the assertion of FRAME_IO.
For more information on how to insert initial latency, see the LogiCORE
PCI User/Design Guides.
Solution 2:
The User application can hold the C_READY output low to insert
wait states during configuration read/writes. A target is
required to complete the first data phase of the transaction
within 16 clock cycles from the assertion of FRAME_IO.
For more information on how to insert initial latency, see the
LogiCORE PCI User/Design guides.
Solution 3:
As a Master, the core behaves in the same way as a Target. It can not
insert subsequent latency, but is compliant in handling a target that
does. It can insert initial latency before the first data phase begins.
The User application can deassert the M_READY output to insert wait
states.
For more information on how to insert initial latency, see the LogiCORE
PCI User/Design guides.
End of Record #4855 - Last Modified: 07/26/99 13:51 |
