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LogiCORE PCI: Target core behavior when the 1st data phase needs more than 16 clocks?
Record #4856
Product Family: Software
Product Line: LogiCore
Product Part: PCI Target
Problem Title:
LogiCORE PCI: Target core behavior when the 1st data phase needs more than 16 clocks?
Problem Description:
Urgency: Standard
General Description:
How does the target CORE behave in the event that the backend
user application logic is not able to the "s_ready" signal for
the first data phase of a PCI transaction of more than 16 clocks?
Does it initiate a Target Termination Sequence on the PCI bus?
Solution 1:
The Xilinx core doesn't automatically terminate the transfer, if the
back end application doesn't assert S_READY within 16 clocks.
This allows the most flexibility to the user.
However, delaying S_READY for a greater amount of time is a
violation of the PCI specification. Though, for some closed
(embedded) systems, this may not be important.
End of Record #4856 - Last Modified: 10/01/99 11:13 |
