Answers Database


1.5i Ngdanno - Timing simulation for ROMs is overly conservative


Record #4861

Product Family: Software

Product Line: FPGA Implementation

Product Part: ngdanno

Product Version: 1.5

Problem Title:

1.5i Ngdanno - Timing simulation for ROMs is overly conservative


Problem Description:
Urgency: High

output delay and not the net delay on the source nets. This results in the timing simulation delays to be to conservative.


Solution 1:

A fix for this problem is included in the 1.5i Service Pack 1. For details
on this Service Pack see http://www.xilinx.com/techdocs/5514.htmInternet Link




End of Record #4861 - Last Modified: 02/02/99 19:06

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Technical Tips!