Answers Database
NGD2VER/NGD2VHDL 1.5: The connection from RAM to LUT are optimized away.
Record #4869
Product Family: Software
Product Line: FPGA Implementation
Product Part: ngd2ver
Product Version: 1.5i
Problem Title:
NGD2VER/NGD2VHDL 1.5: The connection from RAM to LUT are optimized away.
Problem Description:
Urgency: Standard
Signals going from block RAM to LUTs, present in the NCD file are no longer
present after running Ngd2ver/Ngd2vhdl.
Solution 1:
Fixed in A1.5.25.
The problem is in ngd_prep and is exposed when a block RAM output signal
drives a LUT (ROM) input. A function is called on every ROM input pin's signal.
This function is supposed to remove the signal only if it has no driver, but the
block RAM output is not detected as a driver (since it is not an NGD primitive).
Further, this trimming is only supposed to be called when processing an .ngd file
(not an .nga file), but the call for ROMs is made on both file types.
End of Record #4869 - Last Modified: 12/22/99 14:33 |
