Answers Database
VERILOG-XL: SDFA Error: Failed to find HOLD timingcheck.
Record #4872
Problem Title:
VERILOG-XL: SDFA Error: Failed to find HOLD timingcheck.
Problem Description:
Urgency: Standard
General Description: What does "SDFA Error: Failed to find
Hold timingcheck" mean?
Solution 1:
The errors/warnings are due to the TIMINGCHECK properties in
the SDF file not matching the timing checks specified in the
SIMPRIM Verilog models. The SDF file is specified for both
posedge and negedge, but the SIMPRIMS only specify posedge.
A1.5i contains the patched version of the Verilog SIMPRIM
models that include timing checks for both posedge and negedge
edges instead of just one check without any edge qualifier.
Until A1.5i is released, you may download the libraries from
ftp://ftp.xilinx.com/pub/swhelp/M1.5_updates/simprims.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.5_updates/simprims.zip
End of Record #4872 - Last Modified: 06/26/99 15:22 |
