Xilinx Answer #4874 : M1.5 LOGIBLOX: Generates empty Verilog .v simulation models for IN, OUT, and INVERT modules.

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M1.5 LOGIBLOX: Generates empty Verilog .v simulation models for IN, OUT, and INVERT modules.

Record #4874
Product Family: Software

Product Line: FPGA Implementation

Product Part: logiblox

Product Version: 1.5.

Problem Title:

M1.5 LOGIBLOX: Generates empty Verilog .v simulation models for IN, OUT, and INVERT modules.

Problem Description:
Urgency: hot

General Description:
Verilog simulation models generated by LogiBLOX in the M1.5
release for IN and OUT modules are empty.

Solution 1:

LogiBLOX calls NGD2VER to generate the Verilog functional simulation
models for the modules it generates. The problem with the empty
Verilog simulation models for IN, OUT and INVERT modules is
caused by a bug in NGDPREP, a subprogram called by NGD2VER.

The problem can be corrected by disabling the optimizer by
setting the XIL_PP_OPTIMIZE environment variable:

UNIX:
setenv XIL_PP_OPTIMIZE ""

Windows:
set XIL_PP_OPTIMIZE=0

End of Record #4874 - Last Modified: 06/08/99 14:31

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