Answers Database


F1.5, Schematic Editor: Issues involving complex buses; removal of Bus Pin Connection function


Record #4898

Product Family: Software

Product Line: Aldec

Product Part: Foundation Schematic Capture

Problem Title:

F1.5, Schematic Editor:	Issues involving complex buses; removal of Bus Pin Connection
function



Problem Description:
Urgency: Hot

General Description:

In F1.5, changes have been made to the way in which complex buses are
implemented in the Schematic Editor.   The change involved the removal of the Bus Pin Connection
function which was available in F1.4 and was used to define the signal order
for complex buses going into bus pins.	This function was removed because
it is no longer necessary with the new implementation of the complex bus
structures.  Instead of placing the definition of the bus pin order in the Bus
Pin Connection dialog, you now simply place this same definition, or bus
label, on the actual bus segment which is going into the bus pin.   The
Online Help topic "Using Buses" discusses this feature in more detail.

When a design which used the Bus Pin Connection function in F1.4 is
migrated to F1.5, the Bus Pin Connection label is moved down onto the
bus which is connected to the respective bus pin.   The connectivity of the
bus to the bus pin is defined by this label.

A problem exists, however, for some designs which were using the Bus
Pin Connections in F1.4 and are migrated to F1.5. When the Bus Pin
Connection label is moved down to the respective bus, it may rename
the bus with this Bus Pin Connection label, even if the bus had been
labeled differently in F1.4. This causes segments of the bus to have
incorrect labels, and thus the logic in the design to be connected
incorrectly.


Solution 1:

Unfortunately, the only workaround in F1.5 for this problem of bus names
being changed incorrectly during a design migration, is to manually
re-label the buses properly.

This problem is being addressed in F1.5i, and the conversion will be done
properly in this next release.




End of Record #4898 - Last Modified: 01/28/99 12:53

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Technical Tips!