Answers Database
FPGA Express: How to access Carry-In when building arithmetic functions
Record #4981
Product Family: Software
Product Line: Synopsys
Product Part: FPGA Express
Product Version: 2.1.3
Problem Title:
FPGA Express: How to access Carry-In when building arithmetic functions
Problem Description:
Urgency: Standard
General Description:
When creating an adder or subractor with a single bit carry-in signal, one
cannot simply code A + B + Cin (where A and B are N bits wide, and Cin is a
single bit carry in signal), as this will produce two N-bit counters.
Use the following examples to infer a carry-in signal for the carry chain
built by FPGA Express.
Solution 1:
--VHDL Example
--'dummy' signal will be removed
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity add_vhd is
port(a, b : in std_logic_vector(15 downto 0);
cin : in std_logic;
sum : out std_logic_vector(15 downto 0));
end add_vhd;
architecture behav of add_vhd is
signal dummy : std_logic_vector(16 downto 0);
begin
dummy <= (a & cin) + (b & cin);
sum <= tmp(16 downto 1);
end behav;
Solution 2:
//Verilog Example
//'dummy' signal will be removed
module add_v (a, b, cin, sum);
input [15:0] a, b;
input cin;
output [15:0] sum;
wire dummy;
assign {sum, dummy} = {a, cin} + {b, cin};
endmodule
End of Record #4981 - Last Modified: 02/03/99 13:01 |
