Xilinx Answer #4993 : V1.5 COREGEN, VERILOG-XL: "Error! syntax error ... parameter signed =<-" / COREGEN Verilog behavioral models use Verilog-XL reserved word "signed" as a user parameter

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V1.5 COREGEN, VERILOG-XL: "Error! syntax error ... parameter signed =<-" / COREGEN Verilog behavioral models use Verilog-XL reserved word "signed" as a user parameter

Record #4993
Product Family: Software

Product Line: LogiCore

Product Part: Coregen IP Modules

Problem Title:
V1.5 COREGEN, VERILOG-XL: "Error! syntax error ... parameter signed =<-" / COREGEN
Verilog behavioral models use Verilog-XL reserved word "signed" as a user parameter

Problem Description:
Urgency: hot

General Description:

The following error may be seen when loading a COREGEN
Verilog behavioral model involving a signed data
(SDA FIR filters, adders, subtractors, multipliers, etc.):

" Error! syntax error [Verilog] "add20.v", 19: parameter signed =<-"

The syntax error being flagged in the error message is that
the use has illegally specified the Verilog-XL reserved word,
"signed", as one of his user parameters.

The problem line of code in the Coregen behavioral model is
the following:

parameter signed = `true;

Solution 1:

As a workaround, all instances of the word, "signed", where
it is used as a user parameter, should be replaced with a
non-reserved word (for example, "signed_data") using a text editor.

End of Record #4993 - Last Modified: 03/02/99 17:35

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