Answers Database Virtex: Libraries Guide for Output Banking Rules and configuration is incorrect Record #5033 Product Family: Documentation Product Line: FPGA Core Product Part: Libraries Guide Problem Title: Virtex: Libraries Guide for Output Banking Rules and configuration is incorrect Problem Description: Urgency: Standard General Description: In the 1.5 Libraries Guide under the primitive IBUF_selectIO -> SelectI/O Usage Rules -> Ouput Banking (VCCO) Rules, the fourth bullet regarding the configuration pins is incorrect. Solution 1: The following paragraph is from the Libraries Guide: The configuration pins on a Virtex device are on the right side of the chip. When configuring the de vice through a serial prom, the user is required to use a VREF of 3.3V in the two banks on the right   hand side of the chip. If the user is not configuring the device through a serial prom, the VREF re quirement is dependent upon the configuration source. The error is all VREF should be changed to VCCO. The Virtex device can support an input standard that uses a non 3.3 VREF and still be able to accept LVTTL inputs (which are required if interfacing with a SPROM). However, for the Virtex device to drive the pins of the SPROM the VCCO needs to be using a standard that is connected to 3.3V. End of Record #5033 - Last Modified: 11/12/98 15:39

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