Answers Database
A1.5/F1.5 Map - Map drops connection internal to CLB corrupting logic
Record #5053
Product Family: Software
Product Line: FPGA Implementation
Product Part: map
Problem Title:
A1.5/F1.5 Map - Map drops connection internal to CLB corrupting logic
Problem Description:
A case has been seen where map incorrectly configures a CLB where a LUT drives the D inputs of both
flops. One of the flop connections is dropped and the flop is left undriven.
Solution 1:
Work around is to BLKNM the flops to different CLBs:
INST "interface_cfg_out_reg<8>" BLKNM = "FOO" ;
INST "interface_cfg_out_reg<9>" BLKNM = "BAR" ;
Solution 2:
A fix for this problem is included in the 1.5i Service Pack 1. For details
on this Service Pack see http://www.xilinx.com/techdocs/5514.htm
End of Record #5053 - Last Modified: 02/10/99 13:42 | 
