Answers Database
M1.5/Synopsys: FPGA designs containing STARUP/STARTBUF component may not configure properly when using FPGA/Design Compiler for design entry
Record #5063
Product Family: Software
Product Line: Synopsys
Product Part: FPGA Compiler
Problem Title:
M1.5/Synopsys: FPGA designs containing STARUP/STARTBUF component may not configure properly
when using FPGA/Design Compiler for design entry
Problem Description:
Urgency: Hot
When using Synopsys FPGA or Design Compiler with the M1.5 software
and the design has a STARTUP or STARTBUF block instantiated into it
in which the CLK or CLKIN input port to the STARTUP/STARTBUF is
left unconnect, the FPGA may not configure properly using default
M1 options.
Solution 1:
This problem was introduced to M1.5 with a change in default
options for Bitgen. See (Xilinx Solution 4681).
One of the options changed was if there is a signal
connected to the CLK/CLKIN pin of the STARTUP/STARTBUF
component, the device startup clock signal connected to this port
will defaultly be used to intitialize the FPGA. However using FPGA
or Design Compiler, any unconnected input ports to components are
defaultly grounded. If a STARTUP/STARTBUF component is
instantiated and the CLK/CLKIN port is unconnectd, Synopsys will
connect a ground signal to the port. This causes the FPGA to never
"wake up" after configurations unless one of the following is done:
1. Change the StartupClk option in bitgen to Cclk:
bitgen -g StartupClk:Cclk <design>.ncd
This can also be done from the Design Manager Configuration
Options Template.
-- and/or --
2. The Synopsys script may be modified to leave the port
unconnected by doing the following:
a. Connect a net to the CLK/CLKIN port of the instantiated
STARTUP/STARTBUF component in the design. This can be
either described into the HDL code or done from your
Synopsys script.
b. Compile the Design normally leaving this "dummy" signal
connected to the STARTUP/STARTBUF.
c. Before writing out the implementation netlist (.sxnf or
.sedif), perform a disconnect_net -all on the "dummy" net.
This will leave this port unconnected and the design will
implement properly.
End of Record #5063 - Last Modified: 12/02/98 10:02 |
