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M1.5i/Synopsys VSS: Error when compiling UNISIM library: **Error: vhdlan,1073 unisim_VPKG.vhd(509) on function SLV_TO_INT
Record #5070
Problem Title:
M1.5i/Synopsys VSS: Error when compiling UNISIM library: **Error: vhdlan,1073
unisim_VPKG.vhd(509) on function SLV_TO_INT
Problem Description:
Urgency: Standard
While attempting to compile the M1.5i UNISIM libraries using the
Synopsys VSS VHDL simulator the following error may occur:
function SLV_TO_INT(SLV: std_logic_vector
^
**Error: vhdlan,1073 unisim_VPKG.vhd(509):
Subprogram header or deferred constant subtype indication does
not conform to earlier declaration.
function SLV_TO_INT(SLV: std_logic_vector
^
**Error: vhdlan,1072 unisim_VPKG.vhd(509):
Illegal redeclaration of SLV_TO_INT.
Solution 1:
This error is caused by a missing dirction in the SLV_TO_INT
function within the unisim_VPKG.vhd file. If the line 509 in the
unisim_VPKG.vhd is changed
FROM:
function SLV_TO_INT(SLV: std_logic_vector
TO:
function SLV_TO_INT(SLV: in std_logic_vector
The file should be able to be successfully analyzed.
End of Record #5070 - Last Modified: 11/20/98 10:06 |
