Answers Database LogiCORE PCI: All about Zero and One wait states Record #5094 Product Family: Documentation Product Line: PCI Apps Product Part: PCI Frequently Asked Questions Problem Title: LogiCORE PCI: All about Zero and One wait states Problem Description: Urgency: Standard General Description: What is the meaning of zero or one wait state LogiCORE PCI interface and how does that affect timing of the design? Solution 1: The PCI zero wait state interface will not insert any wait states automatically during Initiator Read/Writes. The one wait state interface will insert wait states automatically during Initiator Writes. This typically cuts down the bandwidth by 50% during writes. The timing for Initiator read/write for a zero wait state configuration and Initiator read for a one wait state configuration is identical. Initiator writes occur at one half the speed of Initiator reads in one wait state conficguration. However, an automatic wait state is inserted before the last data phase on zero wait state Initiator burst transactions. This wait state is not inserted on single transfers. The following XC4KXLT devices/packages combinations have zero wait states enabled: PQ208 PQ/HQ240 BG432 ---------------------------------------------------------------------- 4013XLT -1 -1 N/A 4028XLT N/A -09 N/A 4062XLT N/A N/A -09 All other XC4KXLT devices/packages have one wait state enabled. All Spartan Devices/packages have zero wait states enabled. The Ping design, however always downloads with one wait state enabled for all device/package/speed combinations. Setting the CFG[117] bit in the CFG.vhd/.v/.1 file will enable the use of Zero wait states in the LogiCORE interface. Set this bit only if the device, package and speed grade support Zero wait states. The LogiCORE PCI32 4000/Spartan User Guide describes in detail how to change the wait states in the chapter titled "Customizing the LogiCORE PCI Interface". End of Record #5094 - Last Modified: 10/01/99 14:45

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Technical Tips!