Answers Database
M1.5: TRCE: Unconstrained path analysis appears in the middle of the timing report for VIRTEX
Record #5102
Product Family: Software
Product Line: FPGA Implementation
Product Part: trce
Product Version: 1.5i
Problem Title:
M1.5: TRCE: Unconstrained path analysis appears in the middle of the timing report for
VIRTEX
Problem Description:
Urgency: Standard
General Description: Normally the Unconstrained path report is placed at the end of the timing
report. However, constraints applied to the output nets of the DLL are placed in the timing
report after the unconstrained section. This should not cause the user to think that the DLL is
unconstrained. This is simply a formating issue.
Solution 1:
This is fixed in the next release, which is 2.1i.
End of Record #5102 - Last Modified: 05/19/99 14:27 |
