Answers Database
M1.5i/2.1i: TRCE: Confusing constraint header when 4X is invoked with CLKDLL.
Record #5103
Product Family: Software
Product Line: FPGA Implementation
Product Part: trce
Product Version: 1.5i
Problem Title:
M1.5i/2.1i: TRCE: Confusing constraint header when 4X is invoked with CLKDLL.
Problem Description:
Urgency: Standard
General Description: In the Virtex devices it is posible to place two CLKDLLs in a row to
achieve a 4X multiplication of the input clock signal. When a constraint is placed on the input
of the CLKDLL, M1.5i TRCE/TA will create a new constraint for each of the outputs.
After going through the second DLL 2X tap, the constraint header quotes the original
constraint, says that it's multiplying by *2*, then displays the new constraint correctly
multiplied by 4. So the correct constraint is created, but the text in the constraint header is
incorrect and can be confusing.
Solution 1:
This issue will be resolved in a future release of the software.
End of Record #5103 - Last Modified: 07/13/99 15:32 |
