Answers Database
F1.5i Simulator, Virtex: Cannot simulate CLKDLL component in a Timing Simulation.
Record #5124
Product Family: Software
Product Line: Aldec
Product Part: Foundation Logic Simulator
Product Version: 1.5i
Problem Title:
F1.5i Simulator, Virtex: Cannot simulate CLKDLL component in a Timing Simulation.
Problem Description:
Urgency: Standard
General Description:
Simulating CLKDLL in Foundation Simulator 1.5i does not produce any
clock frequency, just a constant value.
Solution 1:
This problem has been corrected for all outputs of the CLKDLL except
the DIVIDE output. This will be resolved in a future software release.
F1.5i Service Pack 2 fixes the other outputs and is available at:
http://support.xilinx.com/support/techsup/sw_updates/
Note: This software update only enable timing simulation of the CLKDLL.
Functional simulation will not work.
End of Record #5124 - Last Modified: 08/05/99 07:23 |
