Answers Database
LogiCORE PCI: PCI Bus Configuration Timing Details
Record #5126
Product Family: Documentation
Product Line: PCI Apps
Product Part: PCI Frequently Asked Questions
Problem Title:
LogiCORE PCI: PCI Bus Configuration Timing Details
Problem Description:
Urgency: Standard
General Description:
How much time does a FPGA have for configuration on a PCI bus?
Solution 1:
V2.2 PCI spec. mandates that the bus should allow 2^25 clock
cycles before being configured. All systems with V2.2 PCI compliant
BIOSes will not have a problem as this is more than enough time for
the FPGA to configure.
The V2.1 PCI spec does not have give guidelines on this issue.
While no conflicts have been reported by V2.1 PCI complaint systems,
Xilinx recommends that a Fast Configuration Mode be used to program
the FPGA.
Solution 2:
FPGAs that are using the 64-bit bus extension are presented with
another problem. The REQ64# signal must be sampled on the
rising edge of RST#.
An ECN has been approved by the PCI SIG, which adds a timing
parameter, Tpvrh. This new parameter guarantees a minimum
time from power valid to the de-assertion of RST#.
The new timing parameter is specified to be a minimum of 100ms.
End of Record #5126 - Last Modified: 01/07/00 14:44 |
