Answers Database
LogiCORE PCI: When is the S_WRDN signal valid?
Record #5128
Product Family: Documentation
Product Line: PCI Apps
Product Part: PCI Frequently Asked Questions
Problem Title:
LogiCORE PCI: When is the S_WRDN signal valid?
Problem Description:
Urgency: Standard
General Description:
The PCI32 user guide says that S_WRDN is valid during ADDR_VLD and
held through the entire transaction. Is it correct?
Solution 1:
S_WRDN is sampled on the next clock after assertion of ADDR_VLD. It
indicates a WRITE, when asserted high (READ, if asserted low).
ADDR_VLD is asserted only during address phase, while S_WRDN remains
at stable value until end of transaction.
End of Record #5128 - Last Modified: 10/01/99 11:13 |
