Answers Database
LogiCORE PCI: Harmless warnings during Cadence Verilog-XL simulation
Record #5134
Product Family: Documentation
Product Line: PCI Apps
Product Part: PCI Frequently Asked Questions
Problem Title:
LogiCORE PCI: Harmless warnings during Cadence Verilog-XL simulation
Problem Description:
Urgency: Standard
General Description:
Cadence Verilog-XL issues the following warning while simulating
the LogiCORE PCI interface.
"/xilinx/xilinx.M1.5/verilog/src/simprims/X_FF.vmd", 71:
Timing violation in
bic_pci_stm.bic_pci_top.\PCI_CORE/PCI_LC/PCI-AD/IO9/IFD/$1I37/X_FF
$setup( IN:298578982, posedge CLK &&& in_clk_enable:298579228, 360:360 );
Is this harmless?
Solution 1:
In order to meet timing, the LogiCORE PCI turns on its AD drivers during
the clock cycle BEFORE it asserts FRAME#. Therefore, the value on AD may
change any time between the start of the clock cycle before FRAME# and
the end of the clock cycle DURING which FRAME# is asserted. If the
change occurs within the setup/hold window around the intermediate clock
edge, a violation will occur when the AD IOB's input FF tries to clock
in the value.
This is harmless since the core does not rely on this indeterminate value.
End of Record #5134 - Last Modified: 10/01/99 11:09 |
