Answers Database
LogiCORE PCI: Is snooping supported?
Record #5159
Product Family: Documentation
Product Line: PCI Apps
Product Part: PCI Frequently Asked Questions
Problem Title:
LogiCORE PCI: Is snooping supported?
Problem Description:
Urgency: Standard
General Description:
What is snooping and is it supported in the LogiCORE PCI interface?
Solution 1:
A general definition of snooping is simply one PCI resource
monitoring a bus cycle, and that resource may either be an active
or passive participant in the bus cycle. An example of an active
resource is the snoop by the cache controller of a PCI master memory
read access cycle and an example of a passive participant is a
graphics card snoop of write access cycles to the VGA chip.
1. When a cache resource is accessed, it is required that the address
on the AD signal lines is compared (snooped) to the address of the
entries in the cache to determine a match (cache hit). The cache
controller in the HOST/PCI BRIDGE drives the SDONE and SBO# signals
to indicate the completion of the snoop and whether a cache hit has
occurred. Both the SDONE and SBO# signals are not supported by the
LogiCORE interface. It is recommended by the PCI spec. that the
systems that do not support cacheble memory, the SDONE and SBO#
signals should be pulled up at the connector.
2. A graphics card must update its color palette every time the PCI
bus master updates the color palette of the VGA chip. The PCI bus
master and the VGA chip complete the write cycle as two bus cycle
participants. The graphics card is is required to monitor and latch
the written palette data simultaneously with or before tha PCI master
and the write cycle terminated the access cycle.
The system BIOS must set the bit 5 in the PCI command register if
VGA palette snooping is supported.
The PCI LogiCORE interface does not support snooping, so the bit 5
is a read only location defined as 0
End of Record #5159 - Last Modified: 01/13/99 16:44 |
