Answers Database
Exemplar: After optimization Spectrum changes my instantiated BUFGDLL to a BUFGP
Record #5192
Product Family: Software
Product Line: Exemplar
Product Part: Leonardo Spectrum
Problem Title:
Exemplar: After optimization Spectrum changes my instantiated BUFGDLL to a BUFGP
Problem Description:
Urgency: Standard
General Description:
I have a Virtex design and I have instantiated the BUFGDLL in my code in
order to utilize the clock dll. After going through 'optimize' the BUFGDLL
is changed to a BUFGP. The BUFGDLL component is still visible after doing
a 'Read'. How do I get synthesis to stop changing the BUFGDLL component to
a BUFGP?
Solution 1:
This is currently being looked at by Exemplar. The workaround for now
is the following:
1) Turn off Clock buffer Insertion
GUI
---
Turn off the option to 'Add Clock Buffers' in the the
Technology -> Advanced Settings tab. Load the library, then process the design
as per ususal.
Command line/Tcl script
-----------------------
Turn off insertion of global buffers before loading the library.
It should look something simliar to the following:
set insert_global_bufs FALSE
load library xcv
.
.
.
2) If Global buffers are needed on signals that Optmize is now NOT automatically
inserting you can issue the following command:
GUI
---
In the 'Constraint' tab click on the 'Input' sub-tab. Select the signal you
wish to insert a buffer on. In the Insert dialogue box is a pulldown menu.
Here you can choose the type of buffer you would like to insert. After
making the appropriate selections select the 'Apply' button. Process the
design are per usual.
Command line/Tcl script
------------------------
To insert a particular buffer on a signal or port name you can do the following:
To insert a BUFGP on a net signal named net_signal_name:
set_attribute -net net_signal_name -name BUFFER_SIG -value BUFGP
To insert a BUFG on a port name name port_signal_name:
set_attribute -port port_signal_name -name BUFFER_SIG -value BUFG
End of Record #5192 - Last Modified: 12/10/98 16:49 |
