Answers Database
LogiCORE PCI: All about master aborts (abnormal terminations)
Record #5193
Product Family: Documentation
Product Line: PCI Apps
Product Part: PCI Frequently Asked Questions
Problem Title:
LogiCORE PCI: All about master aborts (abnormal terminations)
Problem Description:
Urgency: Standard
General Description:
How does the LogiCORE PCI interface handle Master Abort situation?
Solution 1:
A Master may terminate a PCI transaction either when it has
completed its intended transaction, or using a timeout
when the Master's GNT# line is deasserted and its internal
latency timer expired.
The mechanism used for a Master initiated termination is when
FRAME# is deasserted and IRDY# is asserted. This condition
signals to the target that the final data phase is in process.
The final data phase occurs when both IRDY# and TRDY# are
asserted. The transaction reaches completion when both FRAME#
and IRDY# are deasserted (idle state).
The Master may also terminate a transaction when no target
responds. This is known as Master Abort. Typically, after the
Master asserts the FRAME# signal and drives the address onto
AD signal lines, one of the targets can claim the access cycles
by asserting the DEVSEL# signal within a predetermined number
of clock cycles. The earliest a master can abort a transaction
is five clocks after the FRAME# was first sampled asserted.
The master could choose to wait longer than that and must
support the FRAME#--IRDY# relationship on all transactions
including Master aborts. The master must assume that the target
of the access is incapable of dealing with the requested
transaction or the address was bad and must not repeat the
transaction.
A host bus bridge must return all 1's on a read transaction and
discard all the data on a write transaction when terminated with
a master abort. The bridge must set a master abort detected bit
in the status register. Other master devices may report this
condition as an error by signaling the SERR# when the master
can not report that error through its device driver.
The LogiCORE PCI will dessert FRAME_IO after not receiving a
DEVSEL_IO from the addressed target.
The LogiCORE initiator will set the bit CSR[29] if it receives a
master abort on a transaction it initiated. It will also assert
CSR[39] on the clock cycle after the initiator determines that
the addressed target has not responded to the transaction
request. if it detects a Master abort on the PCI bus. The
LogiCORE interface then uses this information to signal to the
state machine that a master abort has occurred.
End of Record #5193 - Last Modified: 10/01/99 11:25 |
