Answers Database
1.5i Map - Virtex mapper fails to pack 2 FMAPs and 2 MUXCY_Ls into one slice.
Record #5201
Product Family: Software
Product Line: FPGA Implementation
Product Part: map
Problem Title:
1.5i Map - Virtex mapper fails to pack 2 FMAPs and 2 MUXCY_Ls into one slice.
Problem Description:
FATAL_ERROR:xvkma:xvkmapper.c:1691:1.112 - Cannot satisfy
LOC/RLOC constraint on comp H29/$I82/$1I55
The errors appear to be due to map trying to suck extra logic in
at the mux inputs. This prevents map from being able to use the
same configuration for both the CY0G and CY0F muxes. The slice can
not support these two muxes in different configurations.
Solution 1:
Keep properties on the MUXCY_L inputs prevent the mapper from
trying to merge too much logic into the slice:
NET "H29/&__A__26" KEEP ;
If GND nets are involved, use a buffer between GND and the MUX
input if possible with a KEEP property on the output net of the
buffer.
This error is being investigated for a possible bug fix.
End of Record #5201 - Last Modified: 12/11/98 10:42 |
