Answers Database
LogiCORE PCI: How does the LogiCORE interface handle single cycle grants?
Record #5202
Product Family: Documentation
Product Line: PCI Apps
Product Part: PCI Frequently Asked Questions
Problem Title:
LogiCORE PCI: How does the LogiCORE interface handle single cycle grants?
Problem Description:
Urgency: Standard
Genral Description:
How does the LogiCORE interface handle single cycle grants?
Solution 1:
The PCI specification states that the the minimum latency
between the assertion of GNT# and FRAME# is one clock cycle.
The PCI interface will not assume bus master-ship if the
GNT_IO signal on the PCI bus is asserted for only one cycle.
If the M_DATA signal is not immediately asserted after the
assertion of M_ADDR_N signal, then a single cycle grant has
occurred.
The LogiCORE interface is unable to assert the FRAME signal
within one clock of GNT_IO being asserted due to a timing issue.
It will only be able to assert FRAME after two clocks. If GNT_IO
was asserted on clock one, and then taken away, a situation may
arise where the arbiter grants the bus to another master on
clock two and the LogiCORE interface and the other master, both
assert FRAME on clock 3. This would cause contention on the bus.
In order to avoid this situation, the LogiCORE requires that the
GNT_IO signal be asserted for atleast two clocks.
If a single cycle grant occurs with the existing PCI logiCORE
interfaces, the user application will need to restart the
transaction attempt. In this sense, a single cycle grant is
similar to a retry from a target occurs.
End of Record #5202 - Last Modified: 10/01/99 11:31 |
