Answers Database
M1.5i/2.1i: TRCE reports large differences in clock delay (skew) on BUFGLS in XV devices
Record #5213
Product Family: Software
Product Line: FPGA Implementation
Product Part: Timing Analyzer
Product Version: 1.5
Problem Title:
M1.5i/2.1i: TRCE reports large differences in clock delay (skew) on BUFGLS in XV devices
Problem Description:
Urgency: Standard
General Description: TRCE reports large delays for specific longlines
in the 4000XV devices.
Solution 1:
In the 1.5i speed files for the XV devices there is an incorrect parameter
value. This causes the delays associated with specific longlines to have
the incorrect delay.
This is can be resolved by installing the latest speed file updates. They
are available on the Xilinx FTP Site:
For the Workstation:
ftp://ftp.xilinx.com/pub/swhelp/M1.5i_updates/15i_sp2_4kxv_data.tar.gz
For the PC:
ftp://ftp.xilinx.com/pub/swhelp/M1.5i_updates/15i_sp2_4kxv_data.exe
End of Record #5213 - Last Modified: 07/13/99 15:22 | 
