Answers Database
LogiCORE PCI: How do the REQ#/GNT#/RST# lines in the LogiCORE interface act?
Record #5229
Product Family: Documentation
Product Line: PCI Apps
Product Part: PCI Frequently Asked Questions
Problem Title:
LogiCORE PCI: How do the REQ#/GNT#/RST# lines in the LogiCORE interface act?
Problem Description:
Urgency: Standard
General Description:
How do the REQ#/GNT#/RST# lines in the LogiCORE interface act?
Solution 1:
PCI bus masters are linked to the central arbiter by individual
request (REQ#) and grant (GNT#) signals. Every master has its
own REQ# and GNT# lines.
A PCI bus master will request ownership of the PCI bus by
asserting the REQ# line when it is immediately ready to begin a
bus transaction. The arbiter will grant access to an agent by
asserting its GNT# line. REQ# is an input to the arbiter while
GNT# is an output.
The REQ# signal must be tri-stated and GNT# ignored when the
RST# signal has been asserted. The arbiter can only perform
arbitration after the RST# line has been deasserted.
The RST# (reset) signal is used to bring PCI-specific registers,
sequencers and signals to a consistent state. Anytime RST# is
asserted, all the PCI output signals must be driven to a benign
state.
The LogiCORE interface uses the REQ_O signal to request access
to the bus. The Initiator may only request the bus when it has
been enabled by setting the Bus Master Enable bit (CSR2). REQ_O
is directly controlled by the REQUEST input from the user
application.
The GNT_I signal is used by the LogiCORE to indicate the arbiter
has granted the bus. Once GNT_I is asserted and REQUEST is
asserted by the user application, the PCI32 interface performs
an Initiator transaction. If GNT_I is asserted and there is not
a pending REQUEST or the Bus Master Enable bit is not set, then
the interface performs bus parking.
The LogiCORE uses RST_I input to reset all internal flip-flops
and force all outputs to a high-impedence state. It Uses the
dedicated global set/reset and global three-state functions of
the FPGA; resets the contents of the Command/Status Register;
disables the Initiator functionality until the system software
sets the Bus Master Enable bit (CSR2) in the Command Register;
disables memory or I/O Target accesses until the system software
sets the Memory Enable or I/O Enable bits in the Command
Register.
The REQUEST line is used by the user application to request a
PCI initiator transaction.The Bus Master Enable bit (CSR2) must
be set in the Command Register before REQUEST has any affect on
the PCI32 interface. This should be done by the system
configuration software. The Initiator func-tionality is disabled
at power-on and after RST_I is asserted. It Should be asserted
at least until the Initiator asserts M_ADDR_N. REQUEST should be
deasserted after the assertion of M_ADDR_N. In most
applications, REQUEST is driven by a set dominant synchronous
set/reset flip-flop. The flip-flop is set by the user
application requesting the bus and reset when the LogiCORE
interface asserts its M_ADDR_N signal. REQUEST can not be kept
asserted all the time.
The signal CNFG_SELF signals the LogiCORE that the configuration
command is intended for the core itself (intended for host
bridge applications). The assertion of CNFG_SELF, high will
override the Master Enable bit (CSR2) as well as perform a
simultaneous Initiator and target transaction to allow the user
application access to the internal LogiCORE configuration space.
CNFG_SELF must be asserted at the same time as REQUEST and must
be kept asserted until the transaction is complete, which is
signalled by the dessertion of M_DATA signal.
The BUS_REQ signal is not supported in this version of the core
and should always be tied low.
End of Record #5229 - Last Modified: 10/01/99 11:29 |
