Answers Database
SYNPLIFY: How to preserve a signal through synthesis using the syn_keep attribute?
Record #5249
Product Family: Software
Product Line: Synplicity
Product Part: Synplify
Product Version: 5.0
Problem Title:
SYNPLIFY: How to preserve a signal through synthesis using the syn_keep attribute?
Problem Description:
Urgency: Standard
General Description: How to preserve a signal or wire through Synplify,
so it does not get optimized?
The syn_keep attribute is declared on a wire or signal. This attribute
preserves the specified wire through synthesis and prevents it from
being optimized out in the final design.
NOTE: Use Synplify 5.0.8 or greater.
Solution 1:
Verilog
-----
module example (<port list>);
wire [7:0] temp /* synthesis syn_keep = 1 */;
Solution 2:
VHDL
-----
library synplify;
use synplify.attributes.all;
entity example is
port ( <port list> )
end entity;
architecture XILINX of example is
signal temp : bit_vector (7 downto 0);
attribute syn_keep of temp : signal is true;
End of Record #5249 - Last Modified: 10/06/99 13:34 |
