Answers Database
NGD2VER 1.5i: dangling signals in Virtex Verilog simulation causes unknowns (stuck at "X")
Record #5262
Product Family: Software
Product Line: FPGA Implementation
Product Part: ngd2ver
Product Version: 1.5i
Problem Title:
NGD2VER 1.5i: dangling signals in Virtex Verilog simulation causes unknowns (stuck at "X")
Problem Description:
Urgency: Hot
General Description: When doing Verilog, Simprim based simulation, X's were
noticed on some output paths and were traced to dangling signals with names
like (NGD2VER_X_4029_1 and NGD2VER_X_4025_1). These nets are inputs
to X_LUT primitives.
Solution 1:
There were a couple of different scenarios that might have caused this problem
(unconnected LUT inputs) which explain the propagation of X's through these
paths.
The two most common causes were:
1) Use of LUT2 components as invertors (generated by Synopsys). The source
design has LUT2's programmed as inverters with the unused input tied to GND.
Map trims the unused input, and then it is left dangling in the simulation
netlist.
2) Use of LUT2/3/4 components with one or more "don't care" inputs (as
defined by the init/equate string) tied to PWR/GND.
The only reasonable workaround in both cases is to not use the NGM file for
simualtion (Deselect "Correlate Simulation Data"). Both of these will be
fixed in the next Xilinx Alliance release (2.1). The NGM file is produced by
Map and used by Ngdanno to correlate back annotation data.
There maybe other possibilites. This is only a problem if the dangling nets
propagate 'X' throughout the simulation. If this is the case, the models have
been written to cover 'X' handling in Alliance 2.1i.
End of Record #5262 - Last Modified: 10/28/99 10:53 | 
