Answers Database
COREGEN, VHDL: Output still available from VHDL behavioral model for area-optimized multiplier when CE is deactivated
Record #5358
Product Family: Software
Product Line: LogiCore
Product Part: Coregen IP Modules
Problem Title:
COREGEN, VHDL: Output still available from VHDL behavioral model for area-optimized
multiplier when CE is deactivated
Problem Description:
Urgency: standard
General Description:
The Area Optimized Multiplier with Coregen are created with a CE pin. According to the datasheet,
this pin should stop all activity within the block (i.e., data should not flow
between the pipeline stages) when it is deasserted. However, when doing a behavioral simulation
with the VHDL model, the CE pin only inhibits data from flowing into the first pipeline stage, but n
ot
between internal stages, and an output is still observed on the multiplier.
Solution 1:
The problem is in the coding of the VHDL model for the multiplier on line 112:
elsif (c'event and rat(c)='1' and rat(c'last_value)='0')
To fix the problem, change line 112 of the COREGEN VHDL model to
include an additional constraint on the CE input:
elsif (c'event and rat(c)='1' and rat(c'last_value)='0' and rat(ce) /='0')
End of Record #5358 - Last Modified: 02/16/99 17:37 |
