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1.5i 4KXL Map - FATAL_ERROR:basnc:basncsignal.c:263:1.67 - Could not find a bel for a signal ...
Record #5363
Product Family: Software
Product Line: FPGA Implementation
Product Part: map
Product Version: 1.5i
Problem Title:
1.5i 4KXL Map - FATAL_ERROR:basnc:basncsignal.c:263:1.67 - Could not find a bel for a signal
...
Problem Description:
Urgency: Standard
General Description: The following error is encountered in Map:
FATAL_ERROR:basnc:basncsignal.c:263:1.67 - Could not find a bel for a signal on
pin F2 of comp CmdProc_U1_ID_PromInterface_U1_timer<0>. Its current
programmed state is : CLKX:CLK ECX:EC CLKY:CLK DY:G G3MUX:G3I G2MUX:COUT0
CARRY:DEC XQMUX:QX YQMUX:QY ECY:EC DX:F SR:C3 EC:C4 FCARRY:CARRY GCARRY:CARRY
G:#LUT:G=((((G4*G2)*G1)+((~G4*~G2)*G1))+((G4*G2)*~G3)+((~G4*~G2)*~G3))+(G1*G3)
F:#LUT:F=((~F3*~F1)+(F3*~F1))+F3 CINMUX:0 SRX:RESET FFX:#FF SRY:RESET
FFY:#FF SETX:SR SETY:SR Process will terminate. Please call Xilinx support.
Solution 1:
Workaround: setenv NO_COLLECT_INVS "" and rerun the mapper.
Two invertors with the same input signal both drive the F LUT of a CLB.
When the invs are merged, the LUT eqn gets corrupted.
Solution 2:
A fix for this problem will be included in version 2.1 which is due to ship in June 1999.
End of Record #5363 - Last Modified: 03/23/99 12:55 |
