Answers Database
FPGA Express: Unlinked modules when black box modules are instantiated. (FE-LINK-2)
Record #5388
Product Family: Software
Product Line: Synopsys
Product Part: FPGA Express
Problem Title:
FPGA Express: Unlinked modules when black box modules are instantiated. (FE-LINK-2)
Problem Description:
Urgency: Standard
General Description
After creating implementation in FPGA Express, the following warning will be produced
if you have instantiated any black box modules in your design. Black boxes can be
LogiBLOX or Coregen modules, or any other netlist that is not synthesized by Express.
Warning: Cannot link cell '...' to its reference design '...'. (FE-LINK-2)
This warning means that FPGA Express does not have access to the module
that you have instatiated. It can not read the reference design for this module
because it is a black box.
Solution 1:
As long as you supply a netlist (XNF, EDIF, NGC, NGO, etc.) for this module,
these warnings can be safely ignored. NGDBUILD (the Translate phase) will
merge these netlists with the top level netlist created by FPGA Express. If there
are any discrepancies between pins, NGDBUILD will let you know.
End of Record #5388 - Last Modified: 06/09/99 09:40 |
