Answers Database
FPGA Express: Warning: No global set/reset (GSR) net can be used in the design .. (FE-GSRMAP-8)
Record #5390
Product Family: Software
Product Line: Synopsys
Product Part: FPGA Express
Problem Title:
FPGA Express: Warning: No global set/reset (GSR) net can be used in the design ..
(FE-GSRMAP-8)
Problem Description:
Urgency: Standard
General Description
When synthesizing a design using FPGA Express, the following warning may be issued:
Warning: No global set / reset (GSR) net could be used in the design because
the design contains the unlinked cell '/<design>-Optimized/<module>'. (FE-GSRMAP-8)
This warning may occur when you instantiate a black box in your design. The black box
can be a LogiBLOX or Coregen module, or any netlist that has not been read into the
FPGA Express project. Because FPGA Express has no knowledge of the synchronous
elements in the black box, it will be unable to determine if there is a single set/reset signal
for the entire design, and will therefore not be able to infer the STARTUP module that will
address the Global Set/Reset needs of the design.
Solution 1:
Two possible solutions exist.
The first is to instantiate the STARTUP module. Simply connect your global set/reset
signal to the GSR pin of STARTUP, and Express will not have to worry about inferring
this component.
The other option is to tell FPGA Express to ignore black boxes when inferring STARTUP.
This is done under the Xilinx Options tab of the Express Constraints Editor. If you check
the box next to "Ignore unlinked cells during GSR mapping", the FPGA Express will only
worry about the set/reset signals connected to synchronous elements that it has access to.
End of Record #5390 - Last Modified: 06/09/99 10:47 |
