Answers Database
1.5i, 2.1i 4KX* Map - Map errors out on carry logic when trimming is disabled.
Record #5394
Product Family: Software
Product Line: FPGA Implementation
Product Part: map
Problem Title:
1.5i, 2.1i 4KX* Map - Map errors out on carry logic when trimming is disabled.
Problem Description:
Cases have been seen where map errors out with incorrect errors related
to carry chain connectivity when trimming is disabled. These cases map
successfully when trimming is not disabled.
ERROR:x4kma:26 - A non-CIN pin on fdce symbol
"iq_iq_adc_i_adc_filt_integrator_1_<16>/I$1"
(output signal=iq_iq_adc_i_adc_filt_integrator_1_<16>)
is driven by signal"iq_iq_adc_i_adc_filt_un20$c15", which
is sourced by the COUT pin of a CY4 component. A COUT pin
can only drive the CIN pin of a CLB.
Solution 1:
This problem can be avoided if unused logic trimming is not disabled.
Incomplete designs can still be mapped successfully if "S" (Save) propertys
are used on the loadless/driverless nets that lead to trimming.
This problem will be corrected in the first major release (as yet unnamed) after version 2.1i.
End of Record #5394 - Last Modified: 06/26/99 14:12 |
