Answers Database
FPGA: Can I drive an IO when there is no power to the device?
Record #5398
Product Family: Hardware
Product Line: 4000
Product Part: 4000
Problem Title:
FPGA: Can I drive an IO when there is no power to the device?
Problem Description:
Urgency: Standard
General Description: What are the affects of driving an IO on an FPGA when there is no power to the
device?
Solution 1:
All 5-V Familes, i.e. 3000, 4000E/EX, 5200, Spartan and all old 3-V familes, i.e. 3000L.
Let's assume that ground is always connected, so we do NOT describe hot plug-in with conventional co
nnectors (that do not guarantee Vcc and ground mating before signal mating).
Each device input has an ESD protection diode pointing from the pin towards the Vcc pin(s). Driving
any pin with a positive signal while Vcc is held rigidly to 0V would result in a lot of current thro
ugh this diode (50 to a 100 mA, depending on the driving source), and is a reliability hazard.
If Vcc is not rigidly held to ground by external loads, then the signal can pull Vcc High, which red
uces the input current, but Vcc might be pulled High enough to start a configuration process, using
the signal pin as an unreliable Vcc source. Bad situation.
Do not drive inputs on 5-V devices while Vcc is Low or 0V.
Solution 2:
All new 3.3-V families ( 5-V tolerant ) 4000XL/XV/XLA/XLT, SpartanXL and also Virtex
The ESD protection is designed differently for these families. It is a 6-V Zener diode directed to
wards ground, not Vcc. Thus, if a pin is driven when the FPGA is not powered up, there is no curren
t until the Zener diode starts conducting at about 6 V.
This means the pins are 5-V tolerant, even when their own Vcc is as low as 0V. It also means that t
here is no requirement for a specific power-up sequence of the different supply voltages.
Note that hot plug-in into standard connectors is a more complicated issue, since signal pins can ma
te before the common ground is established.
End of Record #5398 - Last Modified: 04/23/99 10:03 |
