Answers Database
F1.5 Express: INOUT port declaration synthesized as an output only (FE-PMAP-18)
Record #5405
Product Family: Software
Product Line: Synopsys
Product Part: FPGA Express
Product Version: 2.1.3
Problem Title:
F1.5 Express: INOUT port declaration synthesized as an output only (FE-PMAP-18)
Problem Description:
Urgency: Standard
General Description:
Upon creating an implementation from within FPGA Express for an HDL file with
an INOUT declaration, FPGA Express generates a warning indicating that the
type INOUT is unknown. Then Express infers an OUT type in place of the INOUT.
Solution 1:
Make sure that all signals declared as bidirectional are actually used as both input
and output. See (Xilinx Solution 3296) for more details.
The above warnings usually occur when there are multiple three-state inferences
driving the inout signal. Rather than choosing one three-state to place in the IOB,
Express will place all the three-state using internal TBUFs then use a standard
OBUF at the IOB. Examine your HDL to be sure the bidirectional structure is explicit.
End of Record #5405 - Last Modified: 10/12/99 09:05 |
