Answers Database
LogiCORE PCI: What addressing mode is supported during memory burst transactions?
Record #5441
Product Family: Documentation
Product Line: PCI Apps
Product Part: PCI Frequently Asked Questions
Problem Title:
LogiCORE PCI: What addressing mode is supported during memory burst transactions?
Problem Description:
Urgency: Standard
General Description:
Which addressing mode does Xilinx support, cacheline wrap or linear
incrementing, for memory burst transactions? What happens when an
invalid mode is encountered?
Solution 1:
Xilinx only supports the linear incrementing addressing mode, i.e. the two LSBs
on the AD bus, AD[1:0] must be 00 during memory commands. In linear
incrementing mode, the address is assumed to increment by one DWORD
(4 bytes) for 32-bit transfers and by two DWORDS (8 bytes) for 64-bit transfers.
The PCI interface will issue a disconnect with data after the first data phase if
anything other than the linear incrementing mode is encountered.
End of Record #5441 - Last Modified: 10/01/99 11:08 |
