Answers Database
LogiCORE PCI32 Spartan: How do you use our Spartan core as a target-only core?
Record #5442
Product Family: Documentation
Product Line: PCI Apps
Product Part: PCI Frequently Asked Questions
Problem Title:
LogiCORE PCI32 Spartan: How do you use our Spartan core as a target-only core?
Problem Description:
Urgency: Standard
General Description:
The LogiCORE PCI32 Spartan core is available as master only.
What changes are therefore necessary to convert it to a target-only
core?
Solution 1:
ABOUT THE CSR BITS:
Note that the command registers may still indicate that the core is a
master (as well as other things). This should not affect the core's
operation. In fact, the core requires that the master enable bit be
set in order for timing to be met during implementation. Other bits
worth looking at include the i/o and memory access enable bits.
Section 6.2.2 Device Control of the PCI 2.1 specification,
on page 189 in the first paragraph states:
"Individual bits in the Command register may or may not
be implemented depending on a devices functionality.
For instance, devices that do not implement I/O Space
probably will not implement a writable element at bit
location 0 of the Command Register."
This does not explicitly prohibit ("probably will not") the existence
of a register at bit zero, even if your design does not use I/O space.
The Spartan PCI interface is compliant, based on this passage from
the spec.
Solution 2:
CONVERTING INITIATOR/TARGET TO TARGET-ONLY:
The GNT-, REQ- and IRDY- signals are not used by a target
only interface. Both GNT- and REQ- should be pulled high with
discrete resistors external to the FPGA with a min resistance of
2.42 ohms (as defined by the spec). The input to IRDY-
should be removed so that it never reaches the core.
Without any modifications, the core may hang the system on
a RESET.
To see full documentation on how to convert the Spartan core to
Target-only, see the PCI User's/Design Guide
End of Record #5442 - Last Modified: 10/01/99 14:51 |
